The present application relates to subject matter described in application Ser. No. 09/298,967 filed on Apr. 26, 1999 entitled xe2x80x9cMULTI-PROCESSOR TYPE STORAGE CONTROL APPARATUS FOR PERFORMING ACCESS CONTROL THROUGH SELECTORxe2x80x9d, by Kenji YAMAGAMI, Kazuhisa FUJIMOTO, Yasuo KUROSU and Hisao HONMA, and assigned to the assignee of the present application.
The present invention relates to a controller for controlling a disk array which divides data and stores the data in a plurality of disk drives.
As compared to an I/O performance of a main storage of a computer, an I/O performance of a sub-system using a magnetic disk as a secondary storage has a processing ability inferior by about three to four digits. Reducing this difference, i.e., improving the I/O performance of the sub-system has been tried in various ways.
As one method of improving the I/O performance of a sub-system, a sub-system has been proposed which is constituted of a plurality of disk drives and data is divisionally stored in the disk drives, i.e., a so-called disk array system is known.
For example, according to one conventional technique (hereinafter called a first conventional technique), as shown in FIG. 2, a disk array system is constituted of: a plurality of channel I/F units 111 for executing data transfer between a host computer 101 and a disk array controller 2; a plurality of disk I/F units 112 for executing data transfer between disk drives 120 and the disk array controller 2; cache memory units 115 for temporarily storing data of the disk drives 120; and shared memory units 114 for storing control information on the data in the disk drives 120 and on the disk array controller 2, wherein the cache memory units 115 and shared memory units 114 can be accessed from all of channel I/F units 111 and disk I/F units 112.
According to the first conventional technique, the channel I/F units 111 and disk units I/F units 112 are connected to the shared memory units 114 in one-to-one correspondence, and the channel I/F units 111 and disk units I/F units 112 are also connected to the cache memory units 114 in one-to-one correspondence.
According to another conventional technique (hereinafter called a second conventional technique), as shown in FIG. 3, a disk array system is constituted of: a plurality of channel I/F units 111 for executing data transfer between a host computer 101 and a disk array controller 3; a plurality of disk I/F units 112 for executing data transfer between disk drives 120 and the disk array controller 3; cache memory units 115 for temporarily storing data of the disk drives 120; and shared memory units 114 for storing control information on the data in the disk drives 120 and on the disk array controller 3.
The channel I/F units 111 and disk I/F units 112 are connected to the shared memory units 114 via a shared bus 130, and to the cache memory units 115 via a shared bus 131.
Request for high performance of a disk array system has been dealt with by using a large scale disk array controller and high speed components, e.g., by an increase in the number of processors and in the cache capacity, use of high performance processors, expansion of an internal bus width, improvement on a bus transfer ability and the like.
With the second conventional techniques, however, it is becoming difficult for the transfer ability of an internal bus to follow a large scale system and performance improvement.
In order to achieve a high memory access performance by improving the internal bus performance, it is conceivable that one-to-one correspondence between processors and memories similar to the first conventional technique is preferable.
With this method, the internal bus performance improves proportionally to the number of access paths connected to the memories.
However, the number of access paths connected to shared memories and cache memories increases in proportion to an increase in the number of processors used in the system.
In order to maximize the internal bus performance, it is necessary to efficiently control the accesses between each processor and each memory.
It is an object of the present invention to solve the above-described problem and provide a disk array controller capable of efficiently using access paths between processors and memories and having a high memory access throughput, particularly a high cache memory access throughput.
In order to achieve the above object of the invention, a disk array controller is provided which comprises: one or more interface units to a host computer; one or more interface units to a plurality of disk drives; and one or more physically independent shared memory units for storing control information on data in the disk drives and on the disk array controller, wherein the interface units to the host computer and the interface units to the disk drives can access the shared memory units via a selector, and access paths are connected between the selector and the interface units to the host computer and to the disk drives and between the selector and the shared memory units, and wherein the selector unit includes:
a unit for connecting a plurality of input ports (access paths) from the interface units to the host computer and to the disk drives to a plurality of output ports (access paths) to the shared memory units;
a unit for storing connection requests from input ports to output ports in an arrival order of the connection requests; and
an arbitor unit for arbitrating a plurality of connection requests and assigning an output port to a connection request from an input port.
The arbitor unit assigns, if a top connection request among the connection requests stored in the arrival order is a connection request to a vacant output port, the output port to the connection request; checks a second connection request, if the top connection request among the connection requests stored in the arrival order is a connection request to an occupied output port, and assigns, if the second connection request is a connection request to a vacant output port, the output port to the second connection request; checks a third connection request, if the second connection request is a connection request to an occupied output port, and thereafter repeats an arbitration (assignment) of an output port to a connection request at the most by several times equal to the number of vacant output ports.
In this invention, the shared memory unit includes physically independent and duplicated first and second shared memory units, and the selector accesses both of the first and second shared memory units at the same time.
Also in this invention, the shared memory unit includes a cache memory unit and a shared memory unit both physically divided, the cache memory unit temporarily storing data of the disk drives, and the shared memory unit storing control information on the cache memory unit and the disk array controller;
the selector unit includes first and second selectors both physically independent, the first selector connecting the cache memory unit, and the second selector connecting the shared memory unit;
the disk array controller includes physically independent access paths between the interface units to the host computer and to the disk drives and the cache memory unit or the shared memory unit; and
at least the first selector includes the arbitor unit.
Also in this invention, the shared memory unit includes physically independent and duplicated shared memory units, the shared memory unit includes physically independent and duplicated shared memory units, and at least the selector accesses both the duplicated shared memory units at the same time and is provided with the arbitor unit.
Also in this invention, when the interface units to the host computer or to the disk drives access the shared memory unit or cache memory unit, an address and a command are sequentially transferred, and then after an access path to the shared memory unit or cache memory unit is established, data is transferred.
According to the invention, the selector unit disposed between the interface units to the host computer and to the disk drives and the shared memory units can efficiently distribute access requests from the interface units to the shared memory unit. It is therefore possible to improve throughput of data transfer of the disk array controller.